$1.$ Produce a gate$-$level schematic for a $5-$bit wide carry look$-$ahead adder $($CLA$)$ slice. Also produce a gate$-$level schematic for a carry look$-$ahead generator $($CLG$)$ slice that can input $5$ group propagate and $5$ group generate signals. Produce an architecture diagram that shows how a $125-$bit fast adder can be constructed using your CLA and CLG designs. First determine the critical path through your $125-$bit adder, and then determine the worst$-$case delay through your adder when you assume that $6-$input AND and OR gates are $\backslash (50\backslash \%\backslash )$ slower than AND and OR gates that have $2,3$ or $4$ inputs. $[15$ marks$]$