1. Short Answer a. A VHDL function requires a RETURN statement (Irue)false) (circle the proper answer). b. A VHDL procedure can modify any of its arguments that are mode OUT or INOUT (true/false) (circle the proper answer). c. Is the signal assignment statement in the code shown below legal? Why or why not? subtype BYTE_INT is integer range 0 to 255; variable A_INT: integer:; 22; variable B_INT : BYTE_INT; \( \dot{A}_{\text {_INT }} \) : = B_INT; The smallest physical time delay in VHDL is a The smallest simulation delay is called a An architecture consists of the following parts (check all that apply): - Declarative - Statement Body Generic