Question: 1 . Simulate and Synthesize the following expression. Do not perform any minimization. Use gate - level style System Verilog. Submit the result . zip

1. Simulate and Synthesize the following expression. Do not perform any minimization. Use gate-level style System Verilog. Submit the result.zip file and the screenshots of the simulation waveform and log, and the synthesis. To be eligible for grading, code and testbench must have your name in both headers and also must run. (20 Points) Y=ABCD+ABD+BC

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