$1.$ This indicates which functional unit will write each register, if one exists in Tomasulos algorithm.

a$.$ Register Buffer

b$.$ Register result status

c$.$ Reservation station

d$.$ Common Data bus

$3.$ Hazards by register rotation in Iranium processor are mostly..

a$.$ Control Hazards

b$.$ Structural Hazards

c$.$ None

d$.$ Data Hazards

$4.$ A precise exception cannot happen in the WB stage because

a$.$ at that point the only remaining action is to write to the register file

b$.$ None

c$.$ only a hardware error could trigger an exception.

d$.$ Both options

$6.$ If a program has $40\%$ of its code enhanced to run $2\mathrm{.}3$ times faster. What is the overall system speedup $ $?$

a$.1\mathrm{.}292$

b$.0\mathrm{.}23$

c$.0\mathrm{.}06$

d$.1\mathrm{.}92$

$7.$ This follows out of order execution to speed up the execution of instructions.

a$.$ None

b$.$ Superscalar and Superpipeline

c$.$ Superscalar

d$.$ Superpipeline

$8.$ Systems that do not have parallel processing capabilities are

a$.$ SIMD

b$.$ All options

c$.$ SISD

d$.$ MIMD

$9.$ The stages in the pipelining should get completed within one cycle to$.....$

a$.$ decode instruction in speed

b$.$ increase the speed of performance.

c$.$ fetch the data fast

d$.$ execute the instruction

$12.$ A non$-$pipelined single cycle processor operating at $100MHz$ is converted into a synchronous pipelined processor with five stages requiring $2\mathrm{.}5ns,1\mathrm{.}5ns,2ns,1\mathrm{.}5ns$ and $2\mathrm{.}5ns$ respectively. The delay of the latches is $0\mathrm{.}5sec.$ What is the speed up of the pipeline processor for a large number of instructions?

a$.\frac{10}{3}$

b$.\frac{100}{5}$

c$.\frac{100}{3}$

d$.\frac{3}{10}$

$13.$The pipelining process is also called as

a$.$ None of the mentioned

b$.$ Superscalar operation

c$.$ Von Neumann cycle

d$.$ Assembly line operation

$14.$ Having load before the store in running program order, then interchanging this order, result in a

a$.$ war hazards

b$.$ waw hazard

c$.$ control hazard

d$.$ structural hazard

Question $16$ This system is capable of performing two pipeline stages per clock cycle

a$.$ Super pipeline

b$.$ None

c$.$ Superscalar

d$.$ Superscalar and Super pipeline

$17.$ If an exception is raised and the succeeding instructions are executed completely, then the processor is said to have.

a$.$ Imprecise exceptions

b$.$ Exception handling

c$.$ Error correction

d$.$ None

$15.$ Interrupts which are initiated by an instruction are

a$.$ Software

b$.$ Hardware

C$.$ External

d$.$ Internal

$19.$ Parallel Processing may occur

a$.$ In the clock stream

b$.$ In the data stream

c$.$ In the instruction stream

d$.$ In the instruction and data stream

$20.$ Which one of the following is a characteristic of CISC

a$.$ Instructions are executed by hardware

b$.$ None

c$.$ Fixed format instructions

d$.$ Variable format instructions

$18.$ The cost of a parallel processing is primarily determined by:

a$.$ None

b$.$ Circuit complexity

c$.$ Switching complexity

d$.$ Time complexity