1. Using Behavioural Verilog coding style, write code for JK flip flop that has asynchronous active high reset and works at the falling edge of the clock (negedge)the below circuit (6 points) Hint use case (J. K}) JK Table here JK Q(t+1) Q(1) 0 1 Q (t) 0 0 1 1 0 I 0 1 2. Write test bench for the unit you built in question 1 above, you are to show all possible values for the circuit inputs, your testbench clock time is 20 ns. (3 points) 3. Generate wave form for this test bench (1 point)