Question: Write Verilog code to implement the following state table. Use two always blocks. State changes should occur on the falling edge of the clock. Implement

Write Verilog code to implement the following state table. Use two always blocks. State changes should occur on the falling edge of the clock. Implement the Z₁and Z₂outputs using concurrent conditional statements. Assume that the combinational part of the sequential circuit has a propagation delay of 10ns and the propagation delay between the rising-edge of the clock and the state register output is 5ns.

Next State Present State Output (Z,Z,) 01 X,X, = 00 2 00 10 2 2 01

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