1) Using only two D flip-flops, two full-adders, and additional combinational structures and gates, design the least-significant two bits of a register with the following functionality Control Inputs RST OP OPo Operation Status Outputs 1 if next operation will cause OVER overfow (asynchronous) | | | 0 | 1 | X | Y | Y Y + 1 (increment) | YY-1 (Decrement) | Y 0 (Clear) Y x 2 (Multiply by 2) | 1 0 | 1 | X Note: There are multiple solutions, but solutions using more adders or D flip-flops will be penalized. Use a minimal number of muxes and gates for full credit. The output, OVER, should assume unsigned binary operations (always zero for Load operations). A B OVER