$1.$ What is IEEE $1149\mathrm{.}1$ Standard or JTAG standard? Explain all IEEE $1149.$X standard and

its objective in details.

$2.$ Explain Boundary$-$Scan Chip Architecture

$3.$ How many test cycles are needed to shift a $4-$bit test instruction into the instruction

register of a boundary$-$scan architecture? Assume that you start from the reset state and

that after the instruction is shifted in the TAP will be in the Select$-$DR$-$Scan state.

$4.$ What is MBIST explain static, dynamic and recovery fault in context of the RAM.

$5.$ Explain RAM Fault Simulations and Test Algorithm Generations for the MBIST