Question: 1 ) Your work by hand ( state diagram ) 2 ) Verilog ( . v ) file ( s ) of the light sequence

1) Your work by hand (state diagram)
2) Verilog (.v) file(s) of the light sequence and/or toplevel (if you have one)
3) Verilog (.v) file for testbench of light sequence
4).xdc file
Exam Problem: Design the following light-sequence generator which has
-4 inputs: Clock (Clk), active-high synchronous Reset (Rst), L and R.
-4 outputs: seg_A, seg_B, seg_F, seg_G. The segment \( A \),\( B, F, G(C A, C B, C F, C G)\) of the seven-segment display will be used in this assignment.
- If Rst =1 at the rising edge of Clk , the machine is back at the initial state where all segments are OFF.
- The FSM starts from a state where all segments are OFF.
If the users change their mind about the input signals in the middle of any light sequence, I let you, as a designer, decide how to deal with this - make sure you explain how you deal with this when you draw a state diagram. The segments A -> B -> G -> F -> A -> B -> G ->.... are lit up, one at a time. This sequence is repeated as long as \( L=0\) and \( R=1\).
-(15 pts) Design the circuit (draw its state diagram).
-(30 pts) Write a Verilog file to describe your designed circuit
-(25 pts) Write a testbench to simulate your circuit. Note: your testbench should contain at least 4 case scenarios such as
a)\( L=1, R=0\) for at least 6 clock cycles,
b)\( L=0, R=1\) for at least 6 clock cycles,
c)\( L=1, R=1\) for at least 6 clock cycles,
d) the user changes his/her mind about the input signals in the middle of any light sequence. Your waveform for this case should MATCH with your state diagram!
-(7 pts) Write a top-level code to connect ClkDiv with your designed circuit.
-(8 pts) Write a constraint (.xdc) file for the top-level code and then download your
1 ) Your work by hand ( state diagram ) 2 )

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