Question: 10. Considering address alignment, what is the worst-case time required to fetch a 4-byte operand from a memory with a 60-nsec cycle time and a

10. Considering address alignment, what is the worst-case time required to fetch a 4-byte operand from a memory with a 60-nsec cycle time and a data bus that is 16 bits wide? 11. If the data bus connecting the CPU and memory is 4 bytes wide, how many memory cycles are required to read each of the following from memory? (a) A 16-bit operand read from decimal address 5 (b) A 16-bit operand read from decimal address 15 (c) A 32-bit operand read from decimal address 10 (d) A 32-bit operand read from decimal address 20
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