Question: [10 points] Write a SystemVerilog code for module named count 9 that acts as a counter, counting clock cycles up to 5 and then resetting

[10 points] Write a SystemVerilog code for module named count 9 that acts as a counter, counting clock cycles up to 5 and then resetting to 0 and continuing to count. For full credit organize your code well and use indention to make that organization clear. Your solution should be sufficient, and succinct

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