10.1 For the "burst" read operation, the memory controller FSM of Section 10.2.1 im plicitly specifies that the main system has to activate the rw and mem signals in the first clock cycle and then activate the burst signal in the next clock cycle. We wish to simplify the timing requirement for the main system so that it only needs to issue the command in the first clock cycle (i.c., activates the burst signal at the same time as the rw and mem signals). (a) Revise the state diagram to achieve this goal (b) Convert the state diagram to an ASM chart (c) Derive VHDL code according to the ASM chart