8.2 [M] Consider a main memory built with SDRAM chips. Data are transferred in bursts

as shown in Figure 8.9, except that the burst length is 8. Assume that 32 bits of data are

transferred in parallel. If a 400-MHz clock is used, how much time does it take to transfer:

(a) 32 bytes of data

(b) 64 bytes of data

What is the latency in each case?

Clock R/W RAS CAS Address ROW Col Data Figure 8.9 A burst read of length 4 in an SDRAM. DI D2 D3