11 0116 Which one(s) is/are correct? Select one or more: In ARM Cortex M3, the three phases of instructions executions can be completed in 3 clock cycles for all instructions. In pipelining, it is possible that two instructions are fetched in one clock cycle. In a 3 stage pipeline, the throughput is 3 instructions per cycle. In pipelining, all parts of the hardware are occupied by different instructions In a 5 stage pipelining, the instruction latency will be 5 clock cycles