11) A hardware engineer is designing a multiprocessor system in which each CPU issues on the average one memory request for every instruction and a CPU runs at 500 MIPS max a. How many CPUs will t take to saturate a 500-MHz bus assuming that a memory reference requires one bus cycle? If CPU cache is included in the design assuming cache has 80% hit rate, how many CPUs would take to saturate the bus? b. (Make sure to include explanation in each calculation step)