.11 Astack is a buffer in which the data is stored and retrieved in first-in-last-out fashion. In a synchronous stack, it should consist of the following IO signals: . w.data and r.data: data to be written (also known as pushed) into and read (also known as popped) from the stack. push and pop: control signals to enable the push or pop operation. full and empty: status signals. clk and reset: the clock and reset signals We can use a register file to construct this circuit. by following the design approach of the FIFO buffer. (a) Draw a top-level diagram similar to that in Figure 9.13. (b) Consider a stack of four words. Derive the VHDL code of the control circuit. .11 Astack is a buffer in which the data is stored and retrieved in first-in-last-out fashion. In a synchronous stack, it should consist of the following IO signals: . w.data and r.data: data to be written (also known as pushed) into and read (also known as popped) from the stack. push and pop: control signals to enable the push or pop operation. full and empty: status signals. clk and reset: the clock and reset signals We can use a register file to construct this circuit. by following the design approach of the FIFO buffer. (a) Draw a top-level diagram similar to that in Figure 9.13. (b) Consider a stack of four words. Derive the VHDL code of the control circuit