11:07 learn.bu.edu ..ooo AT&T @ 39% D + Part 3: Efficiency Considerations in CPU Design Exercise 1: 1410] .10 In this exercise, we examine how resource hazards, centrol hazards, and Instruction Set Architecture (ISA) design can affect pipelined execution. Problems in this exercise refer to the following fragment of MIPS code sw r16,12 (r6) 1w r16.8 6) beq rs,r4 . Label # Assurers:" 4 add 5.r Assume that individual pipeline stages have the following latencies 00ps 20ps 50ps 190ps 100ps a. For this problem, assume that all branches are perfectly predicted (this eliminates all control hazards) and that no delay slots are used. If we only have one memory (for both instructions and data), there is a structural hazard every time we need to fetch am instruction in the same cyle in which another instruction accesses data To guarantee forward progress, this hazard must always be resolved in favor of the instruction that accesses sequence in the S-stage pipeline that only has one memory? We have seen that data hazards can be eliminated by adding nops to the code. Can you do the same with this structural hazard? Why? data What is the total execution time b. For this problem, assume that all branches are perfectly predicted (this eliminates all contrel hazards) and that no delay slots are used. Ifwe change load/store instructions to use a register (without an offset) as the address, these instructions no longer need to use the ALLU. As a result, MEM and EX stages can be overlapped and the pipeline has enly 4 stages Change this code to accommodate this changed ISA. Assuming this change does not affect clock cycle time, what speedup is achievesd C. Assuming stall-on-branch and no delay slots, what speedup is achieved on this code if branch outcomes are determined in the ID stage, relative to the esecution where branch outoomes are determined in the EX stage? d. Given these pipeline stage latencles, repeat the speedup calculation from b but take into account the (possible) change in clock cycle time When EX and MEM are done in a single stage, most of their werk can be done in paral el As a result, the resulting EX/MEN stage has a latency that is the larger of the original two, plus 20ps needed for the work that could not be done in parallel e. Given these pipeline stage latencies, repeat the speedup calculation from ctaking into account the (possible) change in clock cydle time. Assume that the latency ID stage increases by 50% and the latency of the EX stage decreases by 10 ps when branch outcome resolution is moved from EX to ID L Assuming stall-on-branch and no delay slots, what is the new clock cydle time and 11:07 learn.bu.edu ..ooo AT&T @ 39% D + Part 3: Efficiency Considerations in CPU Design Exercise 1: 1410] .10 In this exercise, we examine how resource hazards, centrol hazards, and Instruction Set Architecture (ISA) design can affect pipelined execution. Problems in this exercise refer to the following fragment of MIPS code sw r16,12 (r6) 1w r16.8 6) beq rs,r4 . Label # Assurers:" 4 add 5.r Assume that individual pipeline stages have the following latencies 00ps 20ps 50ps 190ps 100ps a. For this problem, assume that all branches are perfectly predicted (this eliminates all control hazards) and that no delay slots are used. If we only have one memory (for both instructions and data), there is a structural hazard every time we need to fetch am instruction in the same cyle in which another instruction accesses data To guarantee forward progress, this hazard must always be resolved in favor of the instruction that accesses sequence in the S-stage pipeline that only has one memory? We have seen that data hazards can be eliminated by adding nops to the code. Can you do the same with this structural hazard? Why? data What is the total execution time b. For this problem, assume that all branches are perfectly predicted (this eliminates all contrel hazards) and that no delay slots are used. Ifwe change load/store instructions to use a register (without an offset) as the address, these instructions no longer need to use the ALLU. As a result, MEM and EX stages can be overlapped and the pipeline has enly 4 stages Change this code to accommodate this changed ISA. Assuming this change does not affect clock cycle time, what speedup is achievesd C. Assuming stall-on-branch and no delay slots, what speedup is achieved on this code if branch outcomes are determined in the ID stage, relative to the esecution where branch outoomes are determined in the EX stage? d. Given these pipeline stage latencles, repeat the speedup calculation from b but take into account the (possible) change in clock cycle time When EX and MEM are done in a single stage, most of their werk can be done in paral el As a result, the resulting EX/MEN stage has a latency that is the larger of the original two, plus 20ps needed for the work that could not be done in parallel e. Given these pipeline stage latencies, repeat the speedup calculation from ctaking into account the (possible) change in clock cydle time. Assume that the latency ID stage increases by 50% and the latency of the EX stage decreases by 10 ps when branch outcome resolution is moved from EX to ID L Assuming stall-on-branch and no delay slots, what is the new clock cydle time and