11:07 learn.bu.edu ..ooo AT&T @ 39% D + Part 2: Instraction Support in CPU Design ire 3: The simple datapath for the cre MIPS aice combines the elements required Exercise 1: 44 44 Problems in this exercise assume that logic blocks needed to implement a processors datapath have the following latencies Extend 200ps 70ps 20ps 90ps 90ps 250ps 15ps 10ps a. If the only thing we need to do in a precessor is fetch consecutive lnstructions (Figure 2), what would the cycle time beT b Consider a datapath similar to the one in Figure 3, but Sor a processor that only has one type of instruction unconditional PC-relative branch.What would the cycle time be for this datapath? c Consider a datapath similar to the one in Figure 3, but for a processor that only has one type of instruction conditional PC-relative branch. What would the cycle time be for this datapath? Question d, e and f refer to the datapath element Shi/Heft-2