> 12 Yll Processor 12 delay [n] yin (n) delay 12 Processor 12 Figure 1: System Diagram for Q1 Here, we have ignored the functionality of the processing block; the delay and the processor blocks are defined as below: w[n] delay z[n] = w[n - 1) win Processor z[n] = w[n] : assume no processing a) Sketch and label carefully y[m] =ya[m] + ve[n) and all intermediate signals specified in Figure 1, xilml-yiml, yalm), Yalm), v3 [m), vz[m].09[n].ven], for the xin Figure 2: [65 marks) 2 1 7 25 -4 -3 -2 -1 0 1 2 3 4 -1 -2 Figure 2: Input Signal xml 1 b) Focusing carefully on your answers in part (a), as an engineer or a computer scientist, how do you interpret the design of this system in two parallel branches in terms of saving time in processing the input information? [5 marks) > 12 Yll Processor 12 delay [n] yin (n) delay 12 Processor 12 Figure 1: System Diagram for Q1 Here, we have ignored the functionality of the processing block; the delay and the processor blocks are defined as below: w[n] delay z[n] = w[n - 1) win Processor z[n] = w[n] : assume no processing a) Sketch and label carefully y[m] =ya[m] + ve[n) and all intermediate signals specified in Figure 1, xilml-yiml, yalm), Yalm), v3 [m), vz[m].09[n].ven], for the xin Figure 2: [65 marks) 2 1 7 25 -4 -3 -2 -1 0 1 2 3 4 -1 -2 Figure 2: Input Signal xml 1 b) Focusing carefully on your answers in part (a), as an engineer or a computer scientist, how do you interpret the design of this system in two parallel branches in terms of saving time in processing the input information? [5 marks)