129.17) in the following processor with 8-bit datapath, there is only one instruction type. Unified (shared) memory address and data buses have 8 bit width. Memory is byte addressable. In the given instruction format, opcode represents the operation code, and func field further describes one of the four ALU operations for the arithmetic/logic instructions. R1 and R2 are operands that describe register addresses. 1 (signed) or A (unsigned) operand size is 8 bits. All read operations from sequentials are asynchronous. All writes are synchronous to clock rising edge (not shown) and depend on enable (en) inputs of the respective sequentials. ALUOUT register is written every cycle, and thus does not require an enable input. Given the ISA details, datapath, and ALU specification for the machine, answer the following questions: a) (2 pts.) What is the maximum number of programmer accessible general purpose registers in the Register file? b) (10 pts.) Sketch a Moore-type state diagram for the Control Unit, trying to minimize the number of states. Do not worry about any start or reset signal. c) (8 pts.) Sketch logic schematic for the Control Unit using one-hot state assignment. d) (5 pts.) What is the size of the Control Memory required to design a microprogrammed control unit for this machine, given the next address generation follows an approach similar to MIPS implementation reviewed in lectures. There is no control decoding logic between Control Memory output and datapath. Show the details of your calculation. e) (10 pts.) Sketch the Control Memory, show its contents and the size of its interface buses. Also show any truth table associated with the microcode sequencer next state logic. bnmbnnbbv zxcmcmzxmcvb vbvnbvnb