14. Which logic circuit of Figure represents the Boolean expression Y = A(BC+D)?

16. The___________ gate output is 1 if one or more of its inputs are 1. 24. Draw a PLC ladder diagram program for the gate logic array shown in Figure. 17. Draw the equivalent gate logic array for the PLC ladder diagram shown in Figure . 18. What will be the data stored in the destination address B3:4 of Figure 4-17 when the input is true? all of these. 20. The address for the point on the I/O module shown in Figure would be: a) I:6/1 c) O:6/1 b) I:1/6 d) O:1/6 21. The address for the point on the I/O module shown in Figure would be: a) I:2/8 c) O:8/2 b) I:8/2 d) O:2/8

23. For the scan process illustrated in figure , step 2 involves: a) solving the ladder program. b) transferring data to the output module. c) transferring data to the input module. d) reading data from the input module. 24. The actual scan time is: a) calculated and stored in the PLC's memory. b) computed each time the END instruction is executed. c) the time taken to scan inputs and outputs and execute the user program. d) all of these.

27. The most likely module address for LS1 of Figure is: a) LS1 I2 b) LS1 O2 c) I:2/2 d) O:2/2 28. The addressing format used with PLCs: a) is standard for all PLCs. b) indicates what PLC input is connected to what input device. c) indicates what PLC output is connected to what output device. d) both b and c.