Question: (15%) [PIPELINE DESIGN] Given a 5-stage pipelined data-path shown as above where register-read is performed at the second stage, ALU computation the third stage, memory

$(15\%) [PIPELINE DESIGN] Given a 5-stage pipelined data-path shown as above$

(15\%) [PIPELINE DESIGN] Given a 5-stage pipelined data-path shown as above where register-read is performed at the second stage, ALU computation the third stage, memory read/write the fourth stage and register write the fifth stage. Consider the following code segment: 1w$3,10($5) lw$3,10($5)add$7,$3,$8sw$9,0($7)add$11,$10,$3add$12,$11,$3beq$9,$11,L1 For the first four instructions of the code segment given above, indicate in which cycle each of the following conditions is true for the 5 -stage pipelined processor: (i) Forward from MEM/WB to ALU input (ii) Forward from EX/MEM to ALU input (iii) Insert pipeline bubble

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