Computer Organization and Design

In the pipelined datapath shown in Figure 1, branch target calculation is done in the ID stage and there is full forwarding support. Answer the questions for the following MIPS code executed by this processor. Assume there is a branch delay slot and registers initially contain the following: ($t1) = 1000000016, ($t9) = 416, ($t0) = 1000000C16. Loop: lw $t2, 0($t1) add $t3, $t2, $s1 add $t1, $t1, $t9 bne $t1, $t0, Loop sw $t3, 0($t1) and $s2, $s4, $s5

(b) In the diagram, identify the cycles that have all five pipeline stages do useful work (i.e. produce results essential for the completion of an instruction)? (c) In Cycle 9, what are the values sent to the register file's port of "Read Register 1", "Read Register 2" and "Write Register" respectively? (d) With the ALU Control specified by Figures 2 and 3, fill in the table below to show the value of control signals in all the pipeline registers at the end of the third cycle. Leave blank any control signals that are not stored in pipeline registers for the given inter- stage buffers.

(e) State the cycles of the diagram in which either ForwardA or ForwardB (as shown in Figure 3) is not 00, and also state the value of ForwardA or ForwardB in those cycles.

Branch PCSrc Hazard Unit ID/EX EX/MEM lyID| Controls, blo MEM/WB Shift aft 2 Rdod Addr 1 Instruction Data egFile dr 2 Memory Read Address Memory AwRead Data Address Write Data rite Dat sig Extond ALU cntrl Forward' Unit Forward Figure I, Pipelined Processor with branch in decode stage Branch PCSrc Hazard Unit ID/EX EX/MEM lyID| Controls, blo MEM/WB Shift aft 2 Rdod Addr 1 Instruction Data egFile dr 2 Memory Read Address Memory AwRead Data Address Write Data rite Dat sig Extond ALU cntrl Forward' Unit Forward Figure I, Pipelined Processor with branch in decode stage