19. Design a D flip-flop circuit with asynchronous Set (S) and Reset (R) inputs using only NAND gates. The flip-flop should: Set its Q output to 1 when S=1 on the rising edge of the clock signal (CLK). Reset its Q output to 0 when R=1 on the rising edge of the clock signal, Have both synchronous and asynchronous behavior. Assume that when both S and R are 1 , the behavior is undefined. Hint: Design the truth table and show the next state