$(20$ points$)[$Structural Hazards$]$

Consider the fragment of MIPS assembly below:

Suppose we modify the pipeline so that it has only one memory $($that handles both

instructions and data$).$ In this case, there will be a structural hazard every time a program

needs to fetch an instruction during the same cycle in which another instruction accesses

data.

a$)$ Draw a pipeline diagram to show where the code above will stall.

b$)$ In general, is it possible to reduce the number of stalls$/$NOPs resulting from this structural

hazard by reordering code?

c$)$ Must this structural hazard be handled in hardware? We have seen that data hazards can

be eliminated by adding NOPs to the code. Can you do the same with this structural

hazard? If so$,$ explain how. If not, explain why not.

d$)$ Using the instruction mix from problem $1,$ approximately how many stalls would you

expect this structural hazard to generate in a typical program?