$2.(10$ pts$)$ After five clock cycles memory goes from state A to state B $($shown below$).$ The table below shows values of the $2-$bit address$($A$[1$:$0]),1-$bit Write$-$Enable and $3-$bit $\backslash ($ D$\_\{\backslash$text $\{$in $\}\}\backslash )$ signals. For each cycle, fill in the missing bits $($represented by dashes$)$