2. [10 points] Assume a byte-addressable computer has 4-KB main memory and 128-byte cache with four blocks, where each block has eight 32-bit words. While executing some program, the CPU reads 32-bit words from the following sequence of 10 addresses (in hexadecimal format): 088 090 250 09C 240 200 220 210 230 080 thend Show the cache contents (e.g., [000] contents stored at address 000) at the end (b) Cache is 2-way set-associative (2 blocks per set) with LRU replacement. (c) Cache is fully-associative with LRU replacement. Cc aoond he coresponding mis rate /vearths 2. [10 points] Assume a byte-addressable computer has 4-KB main memory and 128-byte cache with four blocks, where each block has eight 32-bit words. While executing some program, the CPU reads 32-bit words from the following sequence of 10 addresses (in hexadecimal format): 088 090 250 09C 240 200 220 210 230 080 thend Show the cache contents (e.g., [000] contents stored at address 000) at the end (b) Cache is 2-way set-associative (2 blocks per set) with LRU replacement. (c) Cache is fully-associative with LRU replacement. Cc aoond he coresponding mis rate /vearths