$1.$ A byte addressable computer has a small data cache capable of holding eight $32$bit

words. Each cache block consists of one $32$ bit word. When a given program is

executed the processor reads data from the following sequence of hex addresses:

$211,215,22$A$,20$D$,2$F$5,2$F$1,202,204,219,21$E$,21$A$,20$E

The pattern is repeated four times

a$.$ Show the content of the cache in the $1$st pass, if a direct mapped cache is

used $[3]$

b$.$ find the number of hits, number of miss and the hit rate after the four pass.

$[1+1+1]$

c$.$ A memory system contains a cache, a main memory and a virtual memory. The

access time of the cache is $5$ns$,$ and it has an $80$ percent hit rate. The access

time of the main memory is $100$ ns$,$ and it has a $99\mathrm{.}5$ percent hit rate. The

access time of the virtual memory is $10$ ms$.$ What is the average access time of

the hierarchy.$[3]$

$2.$ Write the control sequence for the following instruction for the single bus organization:

SUB R$1,[$R$2][5$ Marks$]$

$3.$ A magnetic disk drive with $8$ surfaces, $1024$ tracks per surface, and $128$ sectors per track.

Sector size is $1024$ Bytes. The average seek time is $8$ ms$,$ the track$-$to$-$track access time is

$1\mathrm{.}5$ ms$,$ and the drive rotates at $7200$ rpm$.$ Successive tracks in a cylinder can be read

without head movement. What is the average access time? Assume this file is stored in

successive sectors and tracks of successive cylinders, starting at sector $0,$ track $0,$ of

cylinder i$.$ Estimate the time required to transfer a $5-$GB file. $(3+3)$

$4.$ What is the maximum number of one$-$operand instructions that can be supported,

assume an instruction set that uses a fixed $16-$bit instruction length. Operand specifiers

are $6$ bits in length. There are K two$-$operand instructions and L zero$-$operand instructions

Design a variable$-$length opcode to allow all of the following to be encoded in a $36-$bit

instruction:

$$ instructions with two $15-$bit addresses and one $3-$bit register number $(2+2+2)$

$$ instructions with one $15-$bit address and one $3-$bit register number

$$ instructions with no addresses or registers

$5.$ a$.$In the following program segment, identify at least $2$ RAW $($read$-$after$-$write$),$ and $2$ WAR

$($write$-$after$-$read$)$ dependencies and explain them in detail $(2$ X$2=4)$

Instruction$1.$ DIV R$8,$ R$2,$ R$1$

Instruction $2.$ MUL R$6,$ R$4,$ R$8$

Instruction $3.$ ADD R$2,$ R$6,$ R$7$

Instruction $4.$ SUB R$8,$ R$2,$ R$4$

b$.$ A DMA module transferring characters to memory using cycle stealing, from a device

transmitting at $4800$ bps$.$ The processor is fetching instructions at the rate of $106$ instructions

per second. By how much will the processor be slowed down due to the DMA activity? $[3]$

c$.$ The same program is compiled for a CISC machine and for a pipelined $.$The following data

is available:

ICCISC $=500000$ ICRISC $=1100000$ CPICISC $=6\mathrm{.}8$ CPIRISC $=1\mathrm{.}4$

TckCISC $=25$ ns TckRISC $=30$ ns

What is the relative performance of the two machines?$211,215,22$A$,20$D$,2$F$5,2$F$1,202,204,219,21$E$,21$A$,20$E