$2\mathrm{.}2$ Subtask Two

Second, we need to design the logic to control the states $($ON$/$OFF$)$ of each segment in the $7-$Segment display. As

shown in Fig. $3,$ the display contains seven segments labeled through $S_1$ to $S_7.$ When provided with input bit $1,$ a

segment will turn on $($become red$).$ Play with this $7-$Segment display to know the correspondence between the

inputs and the segments.

rig. $3./-$segment vispiay

In this subtask, you will use three input lines $E_0{E}_1{E}_2$ to control the $7-$Segment display. Specifically, $E_0{E}_1{E}_2$

present the binary form of a decimal digit $i(i=0,1,$cdots,$7),$ which will shown in the $7-$Segment display. The

designing process is similar to what you have learned in Lab $10.$ Specially, you will write a truth table with $E_0{E}_1{E}_2$

$,$ Vol. $1,$ No$.1,$ Article $.$ Publication date: April $2024.$

as inputs and $S_1{S}_2{S}_3{S}_4{S}_5{S}_6{S}_7$ as outputs. Carefully decide which segments will be turned ON for each input digit

value. For example, when $i=1,$ we assume that segments $S_4$ and $S_7$ will be turned ON$.$

Based on the truth table, derive the functions relating each output $S_j$ with the inputs $E_0{E}_1{E}_2.$ Finally, construct

the circuit using AND and OR gates. To ease the grading process $($and make the grader happy$),$ you are suggested

to organize the gates as shown in Fig. $4.$

You will use three "Pins" as the inputs $E_0{E}_1{E}_2.$ The figure does not say that there are only three AND

gates and two OR gates in the circuit. You can reuse the AND gates to reduce the number of gates.

$2\mathrm{.}3$ Subtask Three

Now, you can combine the two circuits to achieve our desired functionality: click a button $i,$ show the digit $i$ in

the $7-$Segment display. An example circuit is shown in Fig. $5.$ One thing to notice is that the orders of the bits for

the output of the priority encoder and the input to the rest of the combinational logic might be different. You can

easily adjust the order by modifying the attributes of the priority encoder.