2. (30 pts.) A pipelined 2.5 GHz processor has a memory hierarchy that consists of one level of split cache, one level of unified cache, and a byte addressable main memory. 15% of all instructions are of load/store type while running the relevant benchmark. Some of the properties of the memory hierarchy are provided in the below table: Local Access Time Level Properties (Local Hit Time) 32 kB, 2-way Set Associative Write-Through L1 Instruction IL1 1 clk Cache wih 20% miss rate, and 16 B block size 64 kB, 4-way Set Associative Write-Through L1 Data Cache wih DL1 1 clk 10% miss rate, and 16 B block size 4 MB (222 B), 8-way Set Associative Write-Back L2 Unified Cache UL2 10 clks wih 5% local miss rate, and 32 B block size Main 16 GB DRAM, -0% local miss rate 150 clks Memory a) (5 pts.) Explain the difference between the two different cache write policies covered in the above table, including any SRAM cost. b) (5 pts.) What is the global miss rate of UL2 cache (in %)? c) (7 pts.) What is the average memory access time, AMAT? d) (7 pts.) What is the total SRAM space (in bits) required in UL2 cache to store data, tag, and status information that consists of valid, dirty, and 3 LRU bits to support the eviction policy? e) (6 pts.) Estimate the amount of time spent on memory hierarchy related pipeline stalls if the relevant benchmark used to obtain above statistics has 50 million instructions