Question: 2. [5] Assume a VLIW processor can support one memory references, one floating-point operation, and one integer ALU operation (including branch) per cycle. For the

2. [5] Assume a VLIW processor can support one memory references,

2. [5] Assume a VLIW processor can support one memory references, one floating-point operation, and one integer ALU operation (including branch) per cycle. For the following code, show the VLIW code that unrolls the loop four times. Note: you should schedule the operations to fill the operation slots as much as possible. Assume there are a two-cycle stall between a load and its dependent operation, a two-cycle stall between an integer operation and its dependent branch operation, and a three-cycle stall between a FP operation and its dependent store operation L.D ADD. D S.D DADDUI BNE F6, 0 (R3) F8, FO, F6 F8, 0 (R3) R3, R3, R4, Loop Loop: R3, #8 Answer: 2. [5] Assume a VLIW processor can support one memory references, one floating-point operation, and one integer ALU operation (including branch) per cycle. For the following code, show the VLIW code that unrolls the loop four times. Note: you should schedule the operations to fill the operation slots as much as possible. Assume there are a two-cycle stall between a load and its dependent operation, a two-cycle stall between an integer operation and its dependent branch operation, and a three-cycle stall between a FP operation and its dependent store operation L.D ADD. D S.D DADDUI BNE F6, 0 (R3) F8, FO, F6 F8, 0 (R3) R3, R3, R4, Loop Loop: R3, #8

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