$(25$pts$)$ Given logic expression: f$=$

Design the static complementary gates for the above function.

Draw the gate$-$level logic symbol.

Find one critical path in $($b$)$ and calculate the delay. Assume that the delay through all n$-$input gates are n$,$ delay through an inverter is $1.$

Size the transistors in $($a$)$ so that its rise and fall times are approximately equal. Assume that the effective resistance Rn is $6\mathrm{.}47$k$,$ Rp is $29\mathrm{.}6$ k$,$ and the load of each network is CL$$ Consider the worst case only.

Draw transistor$-$level schematic for domino circuit that implement the above function. Assume that a$,$ a$\text{'},$ b$,$ b$\text{'},$ c$,$ c$\text{'},$ d$,$ d$\text{'}$are all available for the input.

Generate test vectors to check the logic circuits in $($b$)$ for SA$0$ faults and SA$1$ faults at the output. You only need to generate one test vector for each case. Do not enumerate all the input combinations.