$2.$ A $4-$to$-3$ compressor circuit is an adder that receives four equally weighted bits as inputs and produces, as the output, one sum bit and two equally weighted carry$-$out bits. Design an $\backslash (8\backslash$times $8\backslash )$ Wallace tree multiplier that sums up the partial products using half adders, full adders and $4-$to$-3$ compressors. You can express your design in the same simplified graphical way that was used in lecture slide $7-49.$ Your design should minimize the number of levels so that the multiplication delay is minimized while at the same time minimizing the total number of required half adders, plus full adders, plus $4-$to$-3$ compressors. What is that minimum delay if one assumes that the half adders, full adders and $4-$to$-3$ compressors all have an input$-$to$-$output delay of three typical gate delays. Assume that the final adder stage is implemented using a cascade of $4-$bit carry look$-$ahead adder slices, like in lecture slide $7-25.[25$ marks$]$