2. A processor has a clock rate of 2 GHz and executes a program. It has six stages as shown in the table below, with each stage requiring the indicated number of cycles. Note that the time for one cycle is 1/(clock rate).

Instruction Fetch 6 cycles

Instruction Decode 2 cycle

calculate op . 3cycle

Operands Fetch 6 cycles

Operands Execute 3 cycle

instructions Write 5 cycles

a) What is the CPI and MIPS rate of the non-pipelined processor?

b. If the instructions contain 20% branch instructions that impose a 25-cycle penalty each time they branch, what is the best CPI this system can attain?

c. Suppose we introduce branch prediction which works 90% of the time. What CPI can this system attain?

d. If we are able to further improve the processor by making a 2-way superscalar pipeline with same branch prediction rate in d) and with no other hazards, what would the new associated CPI, MIPS rate be and what is the speed-up of this be compared to the non-pipelined processor? Assume millions of instructions are being processed.