A processor has a clock rate of $2GHz$ and executes a program. It has six stages as shown in the table below, with each stage requiring the indicated number of cycles. Note that the time for one cycle is $1/($clock rate$).$

a$)$ What is the CPI and MIPS rate of the non$-$pipelined processor?

b$)$ Suppose this processor can be pipelined. What is the CPI, MIPS rate and speed$-$up of a pipelined version of this processor if no pipeline hazards are encountered?

c$)$ If the instructions contain $20\%$ branch instructions that impose a $20$ cycle penalty each time they branch, what is the resulting CPI of the system?

d$)$ Suppose we introduce branch prediction which works $90\%$ of the time. What is the new CPI of the system?

e$)$ If we are able to further improve the processor by making a $2-$way

superscalar pipeline with same branch prediction rate in d$)$ and with no other hazards, what would the new associated CPI, MIPS rate be and what is the speed$-$up of this be compared to the non$-$pipelined processor?