2. Assume the following assembly instructions are execute on a basic 5-stage pipeline ARM v8 processor STUR X16,(X6, #16] LDUR X16, [x6,#0] SUB X0, X5, X4 XO, label // Assume X5!-X4 ADD X5, x1, x4 SUB X5,X15,x4 For the above code, assume that all branches are perfectly predicted (this eliminates all control hazards) and that no delay slots are used. If we only have one memory (for both instructions and data), there is a structural hazard every time we need to fetch an in instruction in the same cycle in which another instruction accesses data. To guarantee forward progress, this hazard must always be resolved in favor of the instruction that accesses data. What is the total execution time of this instruction sequence in the 5-stage pipeline that only has one memory? We have seen that data hazards can be eliminated by adding NOP to the code. Can you do the same with this structural hazard? Why