$2.$ Assuming that two threads$/$processes are used to execute a code on two separate processors.

for $($ i$=0$; i $<$ N; i$++)\{$

a$[$i$]=$ i;

$\}$

Each processor has its own L$1$ cache with a cache block size of $64$ bytes, and can hold the entire array a$[].$ The work distribution of threads is such that they split the loop in a round robin fashion, e$.$g$.$ thread $0$ on processor $0$ is executing loop i$=0,2,4,6,....$ and thread $1$ on processor $1$ executes the iteration I $=1,3,5,7,,...$ Assuming that the caches of the two processor are using MESI protocol, we would like to analyze an arbitrary interleaving of accesses to the variable a$[]$ among threads.

Consider $2$ interleaving accesses of reads and writes to the array among the processors and illustrate the simulation of the MESI protocol, enumerating the cache state transitions on each processor, the cache controller and the bus, memory messages. You are free to use any format for your illustration of the simulation, but your illustration should include all the above mentioned components.

You can assume that the caches start cold, i$.$e$.,$ all blocks are in INVALID state. $(50$ marks$)$

this is for $50$ marks, so please give very detailed way