2. Cache hierarchy

You are building a computer system with in-order execution that runs at 1 GHz and has a CPI of 1, with no memory accesses. The memory system is a split L1 cache. Both the I-cache and the D-cache are direct mapped and hold 32 KB each, with a block size of 64 bytes.

The memory system is split L1 cache. Both the I-cache and the D-cache are direct mapped and hold 32 KB each, with a block size of 64 bytes.

The I-cache has a 2% miss rate, and the D-cache is a write-through with 5% miss rate.

The hit cycles for both the I-cache and the D-cache take 1 cycle (1 cycle takes 1 ns).

The L2 cache is a unified write-back with a total size of 512 KB and a block size of 64 bytes.

The hit cycle of the L2 cache is 15 cycles. The local hit rate of the L2 cache is 80%.

An L2 data write miss takes extra 15 ns.

Given: Hit time=Hit Rate*Hit Cyles

L2 miss penalty = 100nsec

Compute the AMAT for both instruction and data memories