2. Consider the 2-to-4 decoder: DO DO = b 2-to-4 D1 D1 = b Decoder D2 D2 = ab b D3 D3 = a b a b DO D1 D2 D3 0 0 1 0 0 0 0 1 1 101 0 1 0 0 0 0 1 0 0 0 0 1 Using Verilog, model the decoder at two different design levels: gate level modeling, RTL modeling, or combinational logic modeling. Test your design with four input combinations. In your document, include the design code for both designs, the testbench code, and a screenshot that shows the output for the test cases (display input values, corresponding output values, and time). Also, submit the source code for your design.