2) Continue problem 1 A) Write a System Verilog multiplexer module for your state machine, parameterize input and output array sizes B) Write a System Verilog D register module for your state machine, parameterize input and output array sizes () Write a System Verilog module instantiating your multiplexer and register and using logic to determine output Z. Your inputs should be clock, reset, x, and output should be Z. D) Write a testbench and run it with the sequence x = 000010010101011 and display the inputs (x) and outputs (2) on each positive clock edge to the transcript window E) Port your FSM to Quartus and capture the RTL netlist image