2) CSCE 311 SPRING 2017 Consider a 64 bit machine where physical memory is 64GB a) if we would lke to run processes as large as 64 GB, how many bits would be required for the logical address? Memory b) If we are using page sines of KKB, how many bits are neoded for displacement, or indexing into a page? L) Given following proces fwney puge table, tane set, and instructions, a) Determine the minimam bits necessary to repeesent logical addresses in this system. List the size of each portion(rame and offiet) of a logical address, in bits. Note pages are 4 bytes in c) Ifa single-level page table is used, what is the maximum number of entries in this table? d) How many frames of physikcal memory are required to store a page table? Assume each estry in page taHle is 4B b) Update the values in physical memory to neflect the valoes after the following instructions are carried oat. Show the updated values in physicall memory. Also, list which pages hold values for this process and how this is determined If a two-level page table is used and the outer page table is an 8KB page, how many entries dees it contain, maximally e) Instructions mev rl, 0000 mov r2, 001 add r2, rl mev rl, Mr2, rl mev 011, r2 peg 0000 17 copy memury to negisset, 2 ; add rl to r2 and store in r2 0 How eany bits of the legical address are used to specify an index into the inner page of the 1010ogy memory to negisnet, r10 01 ri to memory 10 : add ri to r2 and store in 12 page table? e Table Page Table 04 04 3) Given a system with a memory access time of 100ss and a disk read access time of Ims and write access tieme of 4ms, a) To keep effective access time within 1 5% of memory access time, how successful mast pager algorithm be that is what is the largest tolerable page-fault rate? 08 b) Considering only swap-in'swap-out time, what is the effective page fault service time for a Page replacement when 70% of papa are dirty? 12 10 15 32 2) CSCE 311 SPRING 2017 Consider a 64 bit machine where physical memory is 64GB a) if we would lke to run processes as large as 64 GB, how many bits would be required for the logical address? Memory b) If we are using page sines of KKB, how many bits are neoded for displacement, or indexing into a page? L) Given following proces fwney puge table, tane set, and instructions, a) Determine the minimam bits necessary to repeesent logical addresses in this system. List the size of each portion(rame and offiet) of a logical address, in bits. Note pages are 4 bytes in c) Ifa single-level page table is used, what is the maximum number of entries in this table? d) How many frames of physikcal memory are required to store a page table? Assume each estry in page taHle is 4B b) Update the values in physical memory to neflect the valoes after the following instructions are carried oat. Show the updated values in physicall memory. Also, list which pages hold values for this process and how this is determined If a two-level page table is used and the outer page table is an 8KB page, how many entries dees it contain, maximally e) Instructions mev rl, 0000 mov r2, 001 add r2, rl mev rl, Mr2, rl mev 011, r2 peg 0000 17 copy memury to negisset, 2 ; add rl to r2 and store in r2 0 How eany bits of the legical address are used to specify an index into the inner page of the 1010ogy memory to negisnet, r10 01 ri to memory 10 : add ri to r2 and store in 12 page table? e Table Page Table 04 04 3) Given a system with a memory access time of 100ss and a disk read access time of Ims and write access tieme of 4ms, a) To keep effective access time within 1 5% of memory access time, how successful mast pager algorithm be that is what is the largest tolerable page-fault rate? 08 b) Considering only swap-in'swap-out time, what is the effective page fault service time for a Page replacement when 70% of papa are dirty? 12 10 15 32