Question: 2 Design a 6-bit shift register using AHDL. The serial data input is 20 ser_in and the outputs are q[5.,0]. It is enabled by an

2 Design a 6-bit shift register using AHDL. The serial data

2 Design a 6-bit shift register using AHDL. The serial data input is 20 ser_in and the outputs are q[5.,0]. It is enabled by an active-HIGH control shift and has a higher priority active-LOW synchronous clear (clear). 2 Design a 6-bit shift register using AHDL. The serial data input is 20 ser_in and the outputs are q[5.,0]. It is enabled by an active-HIGH control shift and has a higher priority active-LOW synchronous clear (clear)

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