$2.$ For a direct$-$mapped cache design with a $64-$bit address, the following shows the bit positions of the address, assuming that the caches are byte$-$addressable.

Tag Index Offset

$63...1514...65...0$

$($a$)$ What is the cache block size?

$($b$)$ How many blocks does the cache have?

$($c$)$ To what block number does the byte address $34368$ map?

$($d$)$ What is the ratio between the total bits required for implementing such a cache over the bits needed for the data storage?