2. Given the following circuit. Draw the timing diagram, explain the steps. B F A D C Given both A and B are changing with time as follows: A=0 at time =0, changed to 1 at time = 10ns, and again back to 0 at time = 35 ns. B 1 at time 0, and changed to 0 at time = 20 ns, and remained the same there after. Plot from time 0 to time 65 ns. Take two little box width = 5 ns in time axis. Assume Gate delays as: = 10 ns for each of OR and NAND gate, and 5 ns for the inverter.