$2.$ If a microprocessor has a cycle time of $0\mathrm{.}3$ nanoseconds, cons, has the processor dock at the fetch cycle is $30\%$ of the processor cycle time, what memory access speed is required to implement load operations with zero wait states and load operations with two wait stales$)$ Processor R is a $64-$bit RISC processor with a $2\mathrm{.}6$ GH clock rate. The average instruction requires one cycle to complete, assuming zero wait state memory accesses. Processor C is a CISC processor with a $2\mathrm{.}1$ GHz clock rate. The average simple instruction requires one cycle to complete, assuming zero wait state memory accesses. The average complex instruction requires two cycles to complete, assuming zero wait state memory accesses. Processor R can't directly implement the complex processing instructions of Processor C$.$ Executing an equivalent set of simple instructions requires an average of three cycles to complete, assuming zero wait state memory accesses.