$2)$ Pipeline Processor and Control hazards

For a $5-$stage pipelined processor, the branch can be resolved in $\backslash (3^\{\backslash$text $\{$th $\}\}\backslash )$ stage.

a$.$ What is the branch penalty $($in clock cycles$)$ if pipeline is stalled until the branch is resolved?

b$.$ Known the ideal CPI for pipelined processor is $1$ and there is NO data hazards and NO structure hazards for this processor. To execute a given program using this pipelined processor, $\backslash (40\backslash \%\backslash )$ of the instructions are branching instructions. Branching prediction was performed and $\backslash (80\backslash \%\backslash )$ of branching instructions are correctly predicted. Pipeline is stalled when the prediction is incorrect and next instruction has to be re$-$fetched. What is the average CPI for this processor executing such a program?

c$.$ Again, suppose there is NO data hazards and NO structure hazards. Without the branch prediction mentioned in b$,$ the CPI of this processor would be ideal CPI $(1$ for a pipelined processor$)+$ average stalls happen at the branching instructions.

Known the CPI in b for this pipelined processor with the branch prediction, what is the speed$-$up for "this pipelined processor with branch prediction" compared with "this pipelined processor without branch prediction"?