2. Structural, data, and control hazards typically require a processor pipeline to stall. Listed below are a series of optimization techniques implemented in a compiler or a processor pipeline designed to reduce or eliminate stalls due to these hazards. For each of the following optimization techniques, state which pipeline hazards it addresses and how it addresses them. Some optimization techniques may address more than one hazard.

(a) Branch prediction

(b) Instruction scheduling

(c) Delay slots

(d) Increasing availability of functional units (ALUs, adders, etc)