Structural, data and control hazards typically require a processor pipeline to stall. Listed below are a series of optimization techniques implemented in a compiler or a processor pipeline designed to reduce or eliminate stalls due to these hazards. For each of the following optimization techniques, state which pipeline hazards it addresses and how it addresses it$.$ Some optimization techniques may address more than one hazard, so be sure to include explanations for all addressed hazards.

$($a$)$ Branch Prediction

A method of resolving a branch hazard that assumes a given outcome for the branch and proceeds from that assumption rather than waiting to ascertain the actual outcome.

$($b$)$ Instruction Scheduling

$($c$)$ delay slots

$($d$)$ increasing availability of functional units $($ALUs$,$ adders etc$)$

$($e$)$ cache