$2.$ The circuit below is a TSPC register. The voltage waveforms of the clock $\backslash ($ C L K $\backslash )$ and the input $\backslash ($ D $\backslash )$ are shown.

$($a$)$ Complete the voltage waveforms at $\backslash ($ X$,$ Q$\_\{$M$\}\backslash )$ and $\backslash ($ Q $\backslash )$ in your answer book. The initial values of these signals are given. Delays can be ignored for simplicity.

$($b$)$ Is this a rising$-$ or falling$-$edge triggered register? Why?

$($c$)$ Simplify this circuit so that it contains fewer transistors. Draw your circuit diagram in the answer book.

$($d$)$ What is the main advantage of this register compared to the one shown in Question $1?$