$2.$ Write down $($a$)$ the state table and $($b$)$ draw the state diagram of the following sequential circuit.

clk input

$3.$ Draw the sequential output $\backslash ($ A $\backslash )$ and $\backslash ($ B $\backslash )$ from the above sequential circuit in $\backslash ($ Q $3\backslash ),$ given the clock and Data inputs timing diagram the same as in Q $2.($Initially$,\backslash (\backslash$mathrm$\{$A$\}=0\backslash )\backslash$& $\backslash (\backslash$mathrm$\{$B$\}=1\backslash ))$